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| M29W160FT M29W160FB M29W320FT M29W320FB 16 Mbit or 32 Mbit (x 8 or x 16, boot block) 3 V supply Flash memory Features Supply voltage - VCC = 2.5 V to 3.6 V (access time: 80 ns) or 2.7 to 3.6 V (access time: 70 ns) for Program, Erase and Read - VPP = 12 V for Fast Program (optional, available in the M29W320FT/B only) Access time: 70, 80 ns Programming time - 10 s per byte/word typical Memory organization: - M29W160FT/B: 35 blocks including 1 boot block (top or bottom location), 2 parameter blocks and 32 main blocks - M29W320FT: 67 blocks including 1 boot block (top or bottom location), 2 parameter blocks and 64 main blocks Program/Erase controller - Embedded byte/word program algorithms Erase Suspend and Resume modes - Read and Program another block during Erase Suspend Unlock Bypass Program command - Faster production/batch programming VPP/WP pin for Fast program and Write Protect (available in the M29W320FT/B only) Temporary block unprotection mode Common Flash interface - 64 bit security code Low power consumption - Standby and Automatic Standby 100,000 Program/Erase cycles per block TSOP48 (N) 12 x 20 mm FBGA TFBGA48 (ZA) 6 x 8 mm Electronic signature - Manufacturer code: 0020h - Top device codes M29W160FT: 22C4h M29W320FT: 22CAh - Bottom device codes M29W160FB: 2249h M29W320FB: 22CBh Automotive device grade 3: - Temperature: -40 to 125 C - Automotive grade certified TSOP48 package is ECOPACK(R) March 2008 Rev 3 1/57 www.numonyx.com 1 Contents M29W160FT, M29W160FB, M29W320FT, M29W320FB Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data input/output or Address input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . 12 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block protection and Blocks unprotection . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 4.2 4.3 4.4 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Contents 4.5 4.6 4.7 4.8 4.9 4.10 4.11 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 5.2 5.3 5.4 5.5 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 7 8 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1 9.2 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3/57 List of tables M29W160FT, M29W160FB, M29W320FT, M29W320FB List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program, Erase times and Program, Erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 24 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, package mechanical data . . 36 TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data . . . . . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Top boot block addresses, M29W160FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Bottom boot block addresses, M29W160FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Top boot block addresses, M29W320FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bottom boot block addresses, M29W320FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M29W160FT/B block addresses (x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M29W320FT/B block addresses (x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M29W160FT/B block addresses (x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 M29W320FT/B block addresses (x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Accelerated Program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, package outline . . . . . . . . . . 36 TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline . . . . . . . . . . . . . . . 37 Programmer equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 In-system equipment block protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 In-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5/57 Description M29W160FT, M29W160FB, M29W320FT, M29W320FB 1 Description The M29W160FT/B and M29W320FT/B are 16 Mbit (2 Mb x 8 or 1 Mb x 16) and 32 Mbit (4 Mb x 8 or 2 Mb x 16) non-volatile memories, respectively. They can be read, erased and reprogrammed. These operations can be performed using a single low voltage supply (2.5 to 3.6 V or 2.7 to 3.6 V for access time of 80 ns and 70 ns, respectively). On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the command interface of the memory. An on-chip Program/Erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Figures 4, 5, 6 and 7, Block addresses. The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32 Kbyte block is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20 mm) and TFBGA48 (0.8 mm pitch) packages. The memory is supplied with all the bits erased (set to '1'). In order to meet environmental requirements, Numonyx offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 6/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 1. Logic diagram VCC VPP/WP(1) Description 15 A0-Amax(2) W E G RP BYTE M29W160FT M29W160FB M29W320FT M29W320FB DQ0-DQ14 DQ15A-1 RB VSS 1. The VPP/WP pin is available in the M29W320FT and M29W320FB only. AI13246 2. Amax is equal to A19 in the M29W160FT/B, and to A20 in the M29W320FT/B. Table 1. Signal names Function Address inputs Data inputs/outputs Data inputs/outputs Data input/output or Address input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy output Byte/word Organization Select VPP/Write Protect Supply voltage Ground Not connected internally Inputs I/O I/O I/O Input Input Input Input Output Input Direction Signal name A0-Amax(1) DQ0-DQ7 DQ8-DQ14 DQ15A-1 E G W RP RB BYTE VPP/WP(2) VCC VSS NC 1. Amax is equal to A19 in the M29W160FT/B, and to A20 in the M29W320FT/B. 2. The VPP/WP pin is available in the M29W320FT and M29W320FB only. 7/57 Description Figure 2. TSOP connections A15 A14 A13 A12 A11 A10 A9 A8 A19 A20/NC(1) W RP NC VPP/WP/NC(2) RB A18 A17 A7 A6 A5 A4 A3 A2 A1 M29W160FT, M29W160FB, M29W320FT, M29W320FB 1 48 M29W160FT M29W160FB 12 37 M29W320FT 13 M29W320FB 36 24 25 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI13247 1. Pin 10 is NC (not connected) in the M29W160FT/B, and it is connected to A20 in the M29W320FT/B. 2. Pin 14 is NC (not connected) in the M29W160FT/B, and it is connected to the VPP/WP pin in the M29W320FT/B. 8/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 3. TFBGA connections (top view through package) 1 2 3 4 5 6 Description A A3 A7 RB W A9 A13 B A4 A17 VPP/ WP(1) RP A8 A12 C A2 A6 A18 NC A10 A14 D A1 A5 A20(2) A19 A11 A15 E A0 DQ0 DQ2 DQ5 DQ7 A16 F E DQ8 DQ10 DQ12 DQ14 BYTE G G DQ9 DQ11 VCC DQ13 DQ15 A-1 H VSS DQ1 DQ3 DQ4 DQ6 VSS AI02985c 1. The above figure gives the TFBGA connections for the M29W320FT/B. On the M29W160FT/B, the VPP/WP pin is NC (not connected). 2. The above figure gives the TFBGA connections for the M29W320FT/B. On the M29W160FT/B, A20 is NC (not connected). 9/57 Description Figure 4. M29W160FT, M29W160FB, M29W320FT, M29W320FB M29W160FT/B block addresses (x 8) M29W160FB Bottom Boot block addresses (x 8) 1FFFFFh 16 Kbyte 1FC000h 1FBFFFh 8 Kbyte 1FA000h 1F9FFFh 8 Kbyte 1F8000h 1F7FFFh 32 Kbyte 1F0000h 1EFFFFh 64 Kbyte 1E0000h 01FFFFh 64 Kbyte 010000h 00FFFFh 32 Kbyte Total of 31 64 Kbyte blocks 01FFFFh 64 Kbyte 010000h 00FFFFh 64 Kbyte 000000h 000000h 004000h 003FFFh 16 Kbyte AI12390b M29W160FT Top Boot block addresses (x 8) 1FFFFFh 64 Kbyte 1F0000h 1EFFFFh 64 Kbyte 1E0000h Total of 31 64 Kbyte blocks 008000h 007FFFh 8 Kbyte 006000h 005FFFh 8 Kbyte 1. Also see Appendix A, Tables 19 and 20 for a full listing of the block addresses. Figure 5. M29W320FT/B block addresses (x 8) M29W320FB Bottom Boot block addresses (x 8) M29W320FT Top Boot block addresses (x 8) 3FFFFFh 16 Kbyte 3FC000h 3FBFFFh 8 Kbyte 3FA000h 3F9FFFh 8 Kbyte 3F8000h 3F7FFFh 32 Kbyte 3F0000h 3EFFFFh 64 Kbyte 3E0000h 3FFFFFh 64 Kbyte 3F0000h 3EFFFFh 64 Kbyte 3E0000h Total of 63 64 Kbyte blocks 01FFFFh 64 Kbyte 010000h 00FFFFh 32 Kbyte Total of 63 64 Kbyte blocks 008000h 007FFFh 8 Kbyte 006000h 005FFFh 8 Kbyte 004000h 003FFFh 16 Kbyte 000000h AI13248b 01FFFFh 64 Kbyte 010000h 00FFFFh 64 Kbyte 000000h 1. Also see Appendix A, Tables 21 and 22 for a full listing of the block addresses. 10/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 6. M29W160FT/B block addresses (x 16) M29W160FB Bottom Boot block addresses (x 16) FFFFFh 8 Kword FE000h FDFFFh 4 Kword FD000h FCFFFh 4 Kword FC000h FBFFFh 16 Kword F8000h F7FFFh 32 Kword F0000h 0FFFFh 32 Kword 08000h 07FFFh 16 Kword Total of 31 32 Kword blocks 0FFFFh 32 Kword 08000h 07FFFh 32 Kword 00000h 00000h 02000h 01FFFh 8 Kword 04000h 03FFFh 4 Kword 03000h 02FFFh 4 Kword F0000h F8000h F7FFFh 32 Kword 32 Kword Description M29W160FT Top Boot block addresses (x 16) FFFFFh Total of 31 32 Kword blocks AI12391b 1. Also see Appendix A, Tables 19 and 20 for a full listing of the block addresses. Figure 7. M29W320FT/B block addresses (x 16) M29W320FB Bottom Boot block addresses (x 16) 1FFFFFh 8 Kword 32 Kword 1F8000h 1F7FFFh 4 Kword 32 Kword 1F0000h 4 Kword Total of 63 32 Kword blocks M29W320FT Top Boot block addresses (x 16) 1FFFFFh 1FE000h 1FDFFFh 1FD000h 1FCFFFh 1FC000h 1FBFFFh 16 Kword 1F8000h 1F7FFFh 32 Kword 1F0000h 00FFFFh 32 Kword 008000h 007FFFh 16 Kword Total of 63 32 Kword blocks 004000h 003FFFh 4 Kword 003000h 002FFFh 4 Kword 002000h 001FFFh 8 Kword 000000h AI13250b 00FFFFh 32 Kword 008000h 007FFFh 32 Kword 000000h 1. Also see Appendix A, Tables 21 and 22 for a full listing of the block addresses. 11/57 Signal descriptions M29W160FT, M29W160FB, M29W320FT, M29W320FB 2 Signal descriptions See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-Amax) Amax is equal to A19 in the M29W160FT/B, and to A20 in the M29W320FT/B. The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase controller. 2.2 Data inputs/outputs (DQ0-DQ7) The Data inputs/outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the command interface of the Program/Erase controller. 2.3 Data inputs/outputs (DQ8-DQ14) The Data inputs/outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. 2.4 Data input/output or Address input (DQ15A-1) When BYTE is High, VIH, this pin behaves as a Data input/output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the word on the other addresses, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data input/output to include this pin when BYTE is High and references to the Address inputs to include this pin when BYTE is Low except when stated explicitly otherwise. 2.5 Chip Enable (E) The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.6 Output Enable (G) The Output Enable, G, controls the Bus Read operation of the memory. 12/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Signal descriptions 2.7 Write Enable (W) The Write Enable, W, controls the Bus Write operation of the memory's command interface. 2.8 VPP/Write Protect (VPP/WP) The VPP/Write Protect pin is only available in the M29W320FT/B devices. It provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Unlock Bypass Program operations. The Write Protect function provides a hardware method of protecting the 16 Kbyte Boot Block. The VPP/Write Protect pin must not be left floating or unconnected. When VPP/Write Protect is Low, VIL, the memory protects the 16 Kbyte Boot Block; Program and Erase operations in this block are ignored while VPP/Write Protect is Low. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the 16 Kbyte Boot Block unless the block is protected using Block Protection. When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the command interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 16. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. A 0.1 F capacitor should be connected between the VPP/Write Protect pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. 2.9 Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all blocks that have been protected. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Section 2.10: Ready/Busy Output (RB), Table 15 and Figure 15., Reset/Temporary Unprotect AC characteristics for more details. Holding RP at VID will temporarily unprotect the protected blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. 13/57 Signal descriptions M29W160FT, M29W160FB, M29W320FT, M29W320FB 2.10 Ready/Busy Output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 15 and Figure 15: Reset/Block Temporary Unprotect AC waveforms. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/Word Organization Select (BYTE) The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8bit mode, when it is High, VIH, the memory is in 16-bit mode. 2.12 VCC supply voltage The VCC supply voltage supplies the power for all operations (Read, Program, Erase etc.). The command interface is disabled when the VCC supply voltage is less than the Lockout voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1 F capacitor should be connected between the VCC supply voltage pin and the VSS ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. 2.13 VSS ground The VSS ground is the reference for all voltage measurements. The two VSS pins of the device must be connected to the system ground. 14/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Bus operations 3 Bus operations There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 2. and Table 3., Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the command interface. A valid Bus Read operation involves setting the desired address on the Address inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data inputs/outputs will output the value, see Figure 12: Read mode AC waveforms, and Table 12: Read AC characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write to the command interface. A valid Bus Write operation begins by setting the desired address on the Address inputs. The Address inputs are latched by the command interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data inputs/outputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 13. and Figure 14., Write AC waveforms, and Tables 13 and 14, Write AC characteristics, for details of the timing requirements. 3.3 Output Disable The Data inputs/outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby When Chip Enable is High, VIH, the memory enters Standby mode and the Data inputs/outputs pins are placed in the high-impedance state. To reduce the supply current to the Standby supply current, ICC2, Chip Enable should be held within VCC 0.2 V. For the Standby current level see Table 11: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase supply current, ICC3, for Program or Erase operations until the operation completes. 3.5 Automatic Standby If CMOS levels (VCC 0.2 V) are used to drive the bus and the bus is inactive for 150 ns or more the memory enters Automatic Standby where the internal supply current is reduced to the Standby supply current, ICC2. The Data inputs/outputs will still output data if a Bus Read operation is in progress. 15/57 Bus operations M29W160FT, M29W160FB, M29W320FT, M29W320FB 3.6 Special bus operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. 3.7 Electronic signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 2. and Table 3, Bus operations. 3.8 Block protection and Blocks unprotection Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. Block Protect and Blocks Unprotect operations are described in Appendix C. Table 2. Bus operations, BYTE = VIL(1) E VIL VIL X VIH VIL G VIL VIH VIH X VIL W VIH VIL VIH X VIH Address inputs DQ15A-1, A0-Amax Cell address Command address X X A0=VIL, A1=VIL, A9=VID, others VIL or VIH A0=VIH, A1=VIL, A9=VID, others VIL or VIH Data inputs/outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data output Data input Hi-Z Hi-Z 20h C4h (M29W160FT) CAh (M29W320FT) 49h (M29W160FB) CBh (M29W320FB) Operation Bus Read Bus Write Output Disable Standby Read manufacturer code Read device code VIL VIL VIH Hi-Z 1. X = VIL or VIH. 16/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 3. Bus operations, BYTE = VIH(1) E VIL VIL X VIH VIL G VIL VIH VIH X VIL W VIH VIL VIH X VIH Address inputs A0-Amax Cell address Command address X X A0=VIL, A1=VIL, A9=VID, others VIL or VIH A0=VIH, A1=VIL, A9=VID, others VIL or VIH Bus operations Operation Bus Read Bus Write Output Disable Standby Read manufacturer code Data inputs/outputs DQ15A-1, DQ14-DQ0 Data output Data input Hi-Z Hi-Z 0020h 22C4h (M29W160FT) 22CAh (M29W320FT) 2249h (M29W160FB) 22CBh (M29W320FB) Read device code VIL VIL VIH 1. X = VIL or VIH. 17/57 Command interface M29W160FT, M29W160FB, M29W320FT, M29W320FB 4 Command interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being used, for a summary of the commands. 4.1 Read/Reset command The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to Read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. 4.2 Auto Select command The Auto Select command is used to read the manufacturer code, the device code and the Block Protection status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. From the Auto Select mode the manufacturer code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The manufacturer code for Numonyx is 0020h. The device code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Block Protection status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-Amax specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data inputs/outputs DQ0-DQ7, otherwise 00h is output. 18/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Command interface 4.3 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data inputs/outputs. See the section on the Status Register for more details. After the program operation has completed the memory returns to the Read mode, unless an error has occurred. When an error occurs the memory continues to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. 4.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. 4.5 Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass mode. See the Program command for details on the behavior. 4.6 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass mode. 19/57 Command interface M29W160FT, M29W160FB, M29W320FT, M29W320FB 4.7 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase command and start the Program/Erase controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data inputs/outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost. 4.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase controller about 50 s after the last Bus Write operation. Once the Program/Erase controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50 s of the last block. The 50 s timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/Erase controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100 s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data inputs/outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. 20/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Command interface 4.9 Erase Suspend command The Erase Suspend command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase controller will suspend within the Erase Suspend Latency time (refer to Table 6 for value) of the Erase Suspend command being issued. Once the Program/Erase controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. 4.10 Erase Resume command The Erase Resume command must be used to restart the Program/Erase controller from Erase Suspend. An erase can be suspended and resumed more than once. 4.11 Read CFI Query command The Read CFI Query command is used to read data from the Common Flash interface (CFI) memory area. This command is valid when the device is in the Read Array mode, or when the device is in Auto Select mode. One Bus Write cycle is required to issue the Read CFI Query command. Once the command is issued subsequent Bus Read operations read from the Common Flash interface memory area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command would be needed if the device is to be put in the Read Array mode from Auto Select mode. See Appendix B, Tables 23, 24, 25, 26, 27 and 28 for details on the information contained in the common flash interface (CFI) memory area. 21/57 Command interface Table 4. M29W160FT, M29W160FB, M29W320FT, M29W320FB Commands, 16-bit mode, BYTE = VIH Bus Write operations(1) (2) (3) Length Command 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset(4) Auto Select Program(6) Unlock Bypass(7) Unlock Bypass Program(6) Unlock Bypass Reset(8) Chip Erase(6) Block Erase(6) Erase Suspend(9) Erase Resume(10) Read CFI Query(11) (5) 1 3 3 4 3 2 2 6 6+ 1 1 1 X 555 555 555 555 X X 555 555 X X 55 F0 AA AA AA AA A0 90 AA AA B0 30 98 2AA 2AA 2AA 2AA PA X 2AA 2AA 55 55 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 X 555 555 555 F0 90 A0 20 PA PD 1. X don't care, PA Program Address, PD Program Data, BA any address in the block. 2. All values in the table are in hexadecimal. 3. The command interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH. 4. After a Read/Reset command, read the memory as normal until another command is issued. 5. After an Auto Select command, read manufacturer ID, device ID or Block Protection status. 6. After this command read the Status Register until the Program/Erase controller completes and the memory returns to Read mode. Add additional blocks during Block Erase command with additional Bus Write operations until Timeout bit is set. 7. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. 8. After the Unlock Bypass Reset command read the memory as normal until another command is issued. 9. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. 10. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/Erase controller completes and the memory returns to Read mode. 11. Command is valid when device is ready to read array data or when device is in Auto Select mode. 22/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 5. Commands, 8-bit mode, BYTE = VIL Bus Write operations(1) (2) (3) Command Length 1st 2nd 3rd 4th Command interface 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read/Reset(4) Auto Select Program(6) Unlock Bypass (7) (5) 1 3 3 4 3 2 2 6 X AAA AAA AAA AAA X X AAA F0 AA AA AA AA A0 90 AA AA B0 30 98 555 555 555 555 PA X 555 555 55 55 55 55 PD 00 55 55 AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA BA 10 30 X AAA AAA AAA F0 90 A0 20 PA PD Unlock Bypass Program(6) Unlock Bypass Reset(8) Chip Erase(6) Block Erase Erase (6) 6+ AAA 1 1 1 X X AA Suspend(9) (10) Erase Resume Read CFI Query(11) 1. X don't care, PA Program Address, PD Program Data, BA any address in the block. 2. All values in the table are in hexadecimal. 3. The command interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8DQ14 and DQ15 are don't care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH. 4. After a Read/Reset command, read the memory as normal until another command is issued. 5. After an Auto Select command, read manufacturer ID, device ID or Block Protection status. 6. After this command read the Status Register until the Program/Erase controller completes and the memory returns to Read mode. Add additional blocks during Block Erase command with additional Bus Write operations until Timeout bit is set. 7. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. 8. After the Unlock Bypass Reset command read the memory as normal until another command is issued. 9. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal. 10. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/Erase controller completes and the memory returns to Read mode. 11. Command is valid when device is ready to read array data or when device is in Auto Select mode. 23/57 Command interface Table 6. M29W160FT, M29W160FB, M29W320FT, M29W320FB Program, Erase times and Program, Erase endurance cycles Parameter Min Typ(1) (2) 29 0.8 20 13 26 13 100,000 20 Max(2) 120(3) 6 (4) (4) Unit s s s s s s cycles years Chip Erase Block Erase (64 Kbytes) Erase Suspend Latency time Program (byte or word) Chip Program (byte by byte) Chip Program (word by word) Program/Erase cycles (per block) Data retention 25 200(3) 120 60 (3) (3) 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC. 24/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Status Register 5 Status Register Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 7: Status Register bits. 5.1 Data Polling bit (DQ7) The Data Polling bit can be used to identify whether the Program/Erase controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling bit will change from a '0' to a '1' when the Program/Erase controller has suspended the Erase operation. Figure 8: Data polling flowchart, gives an example of how to use the Data Polling bit. A Valid address is the address being programmed or an address within the block being erased. 5.2 Toggle bit (DQ6) The Toggle bit can be used to identify whether the Program/Erase controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle bit will output when addressing a cell within a block being erased. The Toggle bit will stop toggling when the Program/Erase controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100s. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 1s. Figure 9: Data toggle flowchart, gives an example of how to use the Data Toggle bit. 25/57 Status Register M29W160FT, M29W160FB, M29W320FT, M29W320FB 5.3 Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase controller. The Error bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1' 5.4 Erase Timer bit (DQ3) The Erase Timer bit can be used to identify the start of Program/Erase controller operation during a Block Erase command. Once the Program/Erase controller starts erasing the Erase Timer bit is set to '1'. Before the Program/Erase controller starts the Erase Timer bit is set to '0' and additional blocks to be erased may be written to the command interface. The Erase Timer bit is output on DQ3 when the Status Register is read. 5.5 Alternative Toggle bit (DQ2) The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error bit to be set the Alternative Toggle bit can be used to identify which block or blocks have caused the error. The Alternative Toggle bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle bit does not change if the addressed block has erased correctly. 26/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 7. Status Register bits(1) Address Any address Any address Any address Any address Erasing block Non-erasing block Erasing block Block Erase Non-erasing block Erasing block Erase Suspend Non-erasing block Good block address Erase Error Faulty block address 1. Unspecified data bits should be ignored. Status Register Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 0 0 1 0 0 0 0 0 0 DQ3 - - - 1 0 0 1 1 - DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle RB 0 0 0 0 0 0 0 0 1 1 Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle 0 0 Figure 8. Data polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO YES DQ5 =1 YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI03598 27/57 Status Register Figure 9. M29W160FT, M29W160FB, M29W320FT, M29W320FB Data toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ6 TWICE DQ6 = TOGGLE YES FAIL NO PASS AI01370C 28/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Maximum rating 6 Maximum rating Stressing the device above the rating listed in Table 8: Absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 8. Symbol TA TBIAS TSTG VIO VCC VID Absolute maximum ratings Parameter Ambient temperature grade 3 Temperature under bias Storage temperature Input or output voltage Supply voltage Identification voltage (1)(2) Min -40 -50 -65 -0.6 -0.6 -0.6 Max 125 125 150 VCC+0.6 4 13.5 Unit C C C V V V 1. Minimum voltage may undershoot to -2 V during transition and for less than 20 ns during transitions. 2. Maximum voltage may overshoot to VCC +2 V during transition and for less than 20 ns during transitions. 29/57 DC and AC parameters M29W160FT, M29W160FB, M29W320FT, M29W320FB 7 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 9: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 9. Operating and AC measurement conditions M29W160FT/B, M29W320FT/B Parameter Min VCC supply voltage Ambient operating temperature (grade 3) Load capacitance (CL) Input rise and fall times Input Pulse voltages Input and output timing ref. voltages 0 to VCC VCC/2 2.7 -40 30 10 0 to VCC VCC/2 70 Max 3.6 125 Min 2.5 -40 30 10 80 Max 3.6 125 V C pF ns V V Unit Figure 10. AC measurement I/O waveform VCC VCC/2 0V AI04498 Figure 11. AC measurement load circuit VCC VCC 25k DEVICE UNDER TEST 25k 0.1F CL CL includes JIG capacitance AI04499 30/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 10. Symbol CIN COUT DC and AC parameters Device capacitance(1) Parameter Input capacitance Output capacitance Test Condition VIN = 0 V VOUT = 0 V Min Max 6 12 Unit pF pF 1. Sampled only, not 100% tested. Table 11. Symbol ILI ILO ICC1 ICC2 ICC3(1) VIL VIH VOL VOH VID IID VLKO DC characteristics Parameter Input Leakage current Output Leakage current Supply current (Read) Supply current (Standby) Supply current (Program/Erase) Input Low voltage Input High voltage Output Low voltage Output High voltage Identification voltage Identification current Program/Erase Lockout supply voltage A9 = VID 1.8 IOL = 1.8 mA IOH = -100 A VCC-0.4 11.5 12.5 100 2.3 Test condition 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIH, f = 6 MHz E = VCC0.2 V, RP = VCC0.2 V Program/Erase controller active -0.5 0.7VCC 4.5 35 Min Typ Max 1 1 10 100 20 0.8 VCC+0.3 0.45 Unit A A mA A mA V V V V V A V 1. Sampled only, not 100% tested. 31/57 DC and AC parameters M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 12. Read mode AC waveforms tAVAV A0-Amax/ A-1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ AI13251 VALID tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID Table 12. Symbol Read AC characteristics M29Wxx0FT/B Alt Parameter Test condition 70 80 80 80 0 80 0 35 25 25 0 ns ns ns ns ns ns ns ns ns E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Unit tAVAV tAVQV tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV tRC tACC tLZ tCE tOLZ tOE tHZ tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Min Max Min Max Min Max Max Max Min 70 70 0 70 0 30 25 25 0 tELFL Chip Enable to BYTE Low or High tELFH tFLQZ BYTE Low to Output Hi-Z tFHQV BYTE High to Output Valid Max Max Max 5 25 30 5 25 30 ns ns ns 1. Sampled only, not 100% tested. 32/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 13. Write AC waveforms, Write Enable controlled tAVAV A0-Amax/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWLWH DC and AC parameters tWHEH tWHGL tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX VCC tVCHEL RB tWHRL AI13252 Table 13. Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL(1) tVCHEL Write AC characteristics, Write Enable controlled M29Wxx0FT/B Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 70 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tOEH tBUSY tVCS Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 30 50 80 80 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit 1. Sampled only, not 100% tested. 33/57 DC and AC parameters M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 14. Write AC waveforms, Chip Enable controlled tAVAV A0-Amax/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH VCC tVCHWL RB tEHRL AI13253 Table 14. Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL(1) tVCHWL Write AC characteristics, Chip Enable controlled M29Wxx0FT/B Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 70 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low tOEH tBUSY tVCS Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 30 50 80 80 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit 1. Sampled only, not 100% tested. 34/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 15. Reset/Block Temporary Unprotect AC waveforms DC and AC parameters W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI02931B Table 15. Symbol tPHWL(1) tPHEL tPHGL(1) tRHWL(1) tRHEL(1) tRHGL(1) tPLPX tPLYH(1) tPHPHH(1) tVHVPP(1) Reset/Block Temporary Unprotect AC characteristics M29Wxx0FT/B Alt Parameter 70 RP High to Write Enable Low, Chip Enable Low, Output Enable Low 80 Unit tRH Min 50 50 ns tRB tRP RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width Min Min Max Min Min 0 500 10 500 250 0 500 10 500 250 ns ns s ns ns tREADY RP Low to Read mode tVIDR RP Rise time to VID VPP Rise and Fall time 1. Sampled only, not 100% tested. Figure 16. Accelerated Program timing waveforms VPP VPP/WP VIL or VIH tVHVPP tVHVPP AI90202 35/57 Package mechanical M29W160FT, M29W160FB, M29W320FT, M29W320FB 8 Package mechanical Figure 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, package outline 1 48 e D1 B 24 25 L1 A2 A E1 E DIE A1 C CP L TSOP-G 1. Drawing is not to scale. Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, package mechanical data millimeters inches Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.4764 0.7953 0.7283 - 0.0276 Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 Min 36/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Package mechanical Figure 18. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package outline Table 17. TFBGA48 6 x 8 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data millimeters inches Max 1.200 0.260 0.900 0.350 6.000 4.000 5.900 - 0.450 6.100 - 0.100 8.000 5.600 0.800 1.000 1.200 0.400 0.400 7.900 - - - - - - 8.100 - - - - - - 0.3150 0.2205 0.0315 0.0394 0.0472 0.0157 0.0157 0.3110 - - - - - - 0.2362 0.1575 0.0138 0.2323 - 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ Min Max 0.0472 Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE Min 37/57 Part numbering M29W160FT, M29W160FB, M29W320FT, M29W320FB 9 Part numbering Table 18. Example: Device type M29 Operating voltage W = VCC = 2.7 to 3.6 V (70 ns), 2.5 to 3.6 V (80 ns) Device function 160F = 16 Mbit (x 8/x 16), Boot block, 0.11 m 320F = 32 Mbit (x 8/x 16), Boot block, 0.11 m Array matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns 80 = 80 ns Package N = TSOP48, 12 x 20 mm ZA = TFBGA48, 6 x 8 mm, 0.80 mm pitch Device grade 3 = Automotive grade certified(1), -40 to 125 C S = Extended voltage range(2), VCC(min) = 2.5 V Option E = ECOPACK(R) Package, Standard Packing F = ECOPACK(R) Package, Tape & Reel Packing 1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. 2. This feature could not be available. Ordering information scheme M29W160FB 70 N 3S E Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 38/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Block address table Appendix A Table 19. # 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Block address table Top boot block addresses, M29W160FT Size (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range (x 8) 1FC000h-1FFFFFh 1FA000h-1FBFFFh 1F8000h-1F9FFFh 1F0000h-1F7FFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh Address range (x 16) FE000h-FFFFFh FD000h-FDFFFh FC000h-FCFFFh F8000h-FBFFFh F0000h-F7FFFh E8000h-EFFFFh E0000h-E7FFFh D8000h-DFFFFh D0000h-D7FFFh C8000h-CFFFFh C0000h-C7FFFh B8000h-BFFFFh B0000h-B7FFFh A8000h-AFFFFh A0000h-A7FFFh 98000h-9FFFFh 90000h-97FFFh 88000h-8FFFFh 80000h-87FFFh 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 00000h-07FFFh 39/57 Block address table Table 20. # 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M29W160FT, M29W160FB, M29W320FT, M29W320FB Bottom boot block addresses, M29W160FB Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 32 8 8 16 Address range (x 8) 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 008000h-00FFFFh 006000h-007FFFh 004000h-005FFFh 000000h-003FFFh Address range (x 16) F8000h-FFFFFh F0000h-F7FFFh E8000h-EFFFFh E0000h-E7FFFh D8000h-DFFFFh D0000h-D7FFFh C8000h-CFFFFh C0000h-C7FFFh B8000h-BFFFFh B0000h-B7FFFh A8000h-AFFFFh A0000h-A7FFFh 98000h-9FFFFh 90000h-97FFFh 88000h-8FFFFh 80000h-87FFFh 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh 03000h-03FFFh 02000h-02FFFh 00000h-01FFFh 40/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 21. # 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Block address table Top boot block addresses, M29W320FT Size (Kbyte/Kword) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address range (x 8) 3FC000h-3FFFFFh 3FA000h-3FBFFFh 3F8000h-3F9FFFh 3F0000h-3F7FFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-18FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh Address range (x 16) 1FE000h-1FFFFFh 1FD000h-1FDFFFh 1FC000h-1FCFFFh 1F8000h-1FBFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 41/57 Block address table Table 21. # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M29W160FT, M29W160FB, M29W320FT, M29W320FB Top boot block addresses, M29W320FT (continued) Size (Kbyte/Kword) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address range (x 8) 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh Address range (x 16) 0F8000h-0FBFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh 42/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 22. # 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Block address table Bottom boot block addresses, M29W320FB Size (Kbyte/Kword) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address range (x 8) 3F0000h-3FFFFFh 3E0000h-3EFFFFh 3D0000h-3DFFFFh 3C0000h-3CFFFFh 3B0000h-3BFFFFh 3A0000h-3AFFFFh 390000h-39FFFFh 380000h-18FFFFh 370000h-37FFFFh 360000h-36FFFFh 350000h-35FFFFh 340000h-34FFFFh 330000h-33FFFFh 320000h-32FFFFh 310000h-31FFFFh 300000h-30FFFFh 2F0000h-2FFFFFh 2E0000h-2EFFFFh 2D0000h-2DFFFFh 2C0000h-2CFFFFh 2B0000h-2BFFFFh 2A0000h-2AFFFFh 290000h-29FFFFh 280000h-28FFFFh 270000h-27FFFFh 260000h-26FFFFh 250000h-25FFFFh 240000h-24FFFFh 230000h-23FFFFh 220000h-22FFFFh 210000h-21FFFFh 200000h-20FFFFh 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh Address range (x 16) 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FBFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 43/57 Block address table Table 22. # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M29W160FT, M29W160FB, M29W320FT, M29W320FB Bottom boot block addresses, M29W320FB (continued) Size (Kbyte/Kword) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address range (x 8) 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 008000h-00FFFFh 006000h-007FFFh 004000h-005FFFh 000000h-003FFFh Address range (x 16) 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 004000h-007FFFh 003000h-003FFFh 002000h-002FFFh 000000h-001FFFh 44/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Common Flash interface (CFI) Appendix B Common Flash interface (CFI) The common flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 23, 24, 25, 26, 27 and 28 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 28: Security code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read command to return to Read mode. Table 23. Query structure overview(1) Sub-section name x 16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI query identification string System interface information Device geometry definition Primary algorithm-specific extended query table Security code area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the primary algorithm (optional) 64 bit unique device number Description Address 1. Query data are always presented on the lowest order data outputs. 45/57 Common Flash interface (CFI) Table 24. Address Data x 16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h M29W160FT, M29W160FB, M29W320FT, M29W320FB CFI query identification string(1) Description Value "Q" Query Unique ASCII String "QRY" "R" "Y" Primary algorithm command set and control interface ID code 16 bit ID code defining a specific algorithm Address for primary algorithm extended query table (see Table 27) Alternate vendor command set and control interface id code second vendor - specified algorithm supported Address for alternate algorithm extended query table AMD Compatible P = 40h NA NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'. 46/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 25. Address Data x 16 x8 VCC logic supply minimum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VCC logic supply maximum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV Description Common Flash interface (CFI) CFI query system interface information Value 1Bh 36h 0027h 2.7 V 1Ch 38h 0036h 3.6 V NA 11.5 V NA 12.5 V 16 s n 0000h M29W160FT/B 1Dh 3Ah 00B5h M29W320FT/B 0000h M29W160FT/B 1Eh 3Ch 00C5h M29W320FT/B 1Fh 20h 21h 22h 23h 24h 25h 26h 3Eh 40h 42h 44h 46h 0005h M29W320FT/B 48h 4Ah 0004h M29W320FT/B 4Ch VPP [programming] supply minimum Program/Erase voltage VPP [programming] supply minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP [programming] supply maximum Program/Erase voltage VPP [programming] supply maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 0004h Typical timeout per single byte/word program = 2n s 0000h Typical timeout for minimum size write buffer program = 2 s 000Ah Typical timeout per individual block erase = 2 ms 0000h Typical timeout for full chip erase = 0004h M29W160FT/B 2n ms n NA 1s NA 256 s 512 s NA 2n times typical 8s 16 s NA Maximum timeout for byte/word program = 2n times typical Maximum timeout for byte/word program = 2 times typical 2n times typical n 0000h Maximum timeout for write buffer program = 0003h M29W160FT/B Maximum timeout per individual block erase = Maximum timeout per individual block erase = 2n times typical 2n times typical 0000h Maximum timeout for chip erase = 47/57 Common Flash interface (CFI) Table 26. Address Data x 16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h x8 M29W160FT, M29W160FB, M29W320FT, M29W320FB Device geometry definition Description Value 2 Mbyte 4 Mbyte x 8, x 16 Async. NA 0015h M29W160FT/B device size = 2n in number of bytes 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 0016h M29W320FT/B device size = 2 in number of bytes 0002h Flash device interface code description 0000h 0000h Maximum number of bytes in multi-byte program or page = 2n 0000h Number of Erase Block Regions within the device. 0004h It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. 0000h Region 1 information 0000h Number of identical size erase block = 0000h+1 0040h Region 1 information 0000h Block size in Region 1 = 0040h * 256 byte 0001h Region 2 information 0000h Number of identical size erase block = 0001h+1 0020h Region 2 information 0000h Block size in Region 2 = 0020h * 256 byte 0000h Region 3 information 0000h Number of identical size erase block = 0000h+1 0080h Region 3 Information 0000h Block size in Region 3 = 0080h * 256 byte 001Eh M29W160FT/B Region 4 information 0000h Number of identical-size erase block = 001Eh+1 003Eh M29W320FT/B Region 4 information 0000h Number of identical-size erase block = 003Eh+1 0000h Region 4 information 0001h Block size in Region 4 = 0100h * 256 byte n 4 1 16 Kbyte 2 8 Kbyte 1 32 Kbyte 31 63 64 Kbyte 39h 3Ah 72h 74h 3Bh 3Ch 76h 78h 48/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 27. Common Flash interface (CFI) Primary algorithm-specific extended query table Data Description Value "P" "R" "I" "1" "0" Yes Address x 16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h Primary algorithm extended query table unique ASCII string 0052h "PRI" 0049h 0031h Major version number, ASCII 0030h Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 0000h 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) 0002h 0001h 0001h 0004h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of blocks in per group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 04 = M29W400B 46h 47h 48h 49h 4Ah 4Bh 4Ch 8Ch 8Eh 90h 92h 94h 96h 98h 2 1 Yes 4 No No No 0000h Simultaneous operations, 00 = not supported 0000h Burst mode, 00 = not supported, 01 = supported 0000h Page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word 4Dh(1) 9Ah VPP supply minimum Program/Erase voltage 00B5h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP supply minimum Program/Erase voltage 00C5h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 000xh Top/Bottom Boot Block Flag 02h = Bottom Boot device, 03h = Top Boot device 11.5 V 4Eh (1) 9Ch 12.5 V 4Fh(1) 9Eh - 1. Only for the M29W320FT/B devices. Table 28. Security code area Data Description Address x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX 49/57 Block protection M29W160FT, M29W160FB, M29W320FT, M29W320FB Appendix C Block protection Block protection can be used to prevent any operation from modifying the data stored in the Flash memory. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the signal descriptions section. Unlike the command interface of the Program/Erase controller, the techniques for protecting and unprotecting blocks could change between different Flash memory suppliers. 9.1 Programmer technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a block follow the flowchart in Figure 19: Programmer equipment block protect flowchart. During the Block Protect algorithm, the Amax-A12 address inputs indicate the address of the block to be protected. The block will be correctly protected only if Amax-A12 remain valid and stable, and if Chip Enable is kept Low, VIL, all along the Protect and Verify phases. The Chip Unprotect algorithm is used to unprotect all the memory blocks at the same time. This algorithm can only be used if all of the blocks are protected first. To unprotect the chip follow Figure 20: Programmer equipment chip unprotect flowchart. Table 29: Programmer technique bus operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 9.2 In-system technique The in-system technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash memory has been fitted to the system. To protect a block follow the flowchart in Figure 21: In-system equipment block protect flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 22: Insystem equipment chip unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 50/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Table 29. Operation Block protection Programmer technique bus operations, BYTE = VIH or VIL E G W Address inputs A0-Amax A9 = VID, A12-Amax Block Address Others = X A9 = VID, A12 = VIH, A15 = VIH Others = X A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-Amax Block Address Others = X A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-Amax Block Address Others = X Data inputs/outputs DQ15A-1, DQ14-DQ0 Block Protect VIL VID VIL Pulse X Chip Unprotect VID VID VIL Pulse X Block Protection VIL Verify VIL VIH Pass = XX01h Retry = XX00h Block Unprotection Verify VIL VIL VIH Retry = XX01h Pass = XX00h 51/57 Block protection M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 19. Programmer equipment block protect flowchart START ADDRESS = BLOCK ADDRESS Set-up W = VIH n=0 G, A9 = VID, E = VIL Wait 4 s Protect W = VIL(1) Wait 100 s W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL(1) Wait 4 s G = VIL Wait 60 ns Read DATA Verify DATA NO = 01h YES A9 = VIH E, G = VIH ++n = 25 YES NO End PASS A9 = VIH E, G = VIH FAIL AI03469b 1. Address inputs Amax-A12 give the address of the block that is to be protected. It is imperative that they remain stable during the operation. 2. During the Protect and Verify phases of the algorithm, Chip Enable E must be kept Low, VIL. 52/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 20. Programmer equipment chip unprotect flowchart START PROTECT ALL BLOCKS Block protection Set-up n=0 CURRENT BLOCK = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Wait 4 s Unprotect W = VIL Wait 10 ms W = VIH E, G = VIH ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1, A6 = VIH E = VIL Wait 4 s G = VIL INCREMENT CURRENT BLOCK Verify Wait 60 ns Read DATA NO DATA = 00h YES NO ++n = 1000 YES LAST BLOCK YES A9 = VIH E, G = VIH PASS NO End A9 = VIH E, G = VIH FAIL AI03470 53/57 Block protection M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 21. In-system equipment block protect flowchart START Set-up n=0 RP = VID WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Protect WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 100 s WRITE 40h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Verify Wait 4 s READ DATA ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL DATA NO = 01h YES RP = VIH End ++n = 25 YES RP = VIH NO ISSUE READ/RESET COMMAND PASS ISSUE READ/RESET COMMAND FAIL AI03471 54/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Figure 22. In-system equipment chip unprotect flowchart START PROTECT ALL BLOCKS Block protection Set-up n=0 CURRENT BLOCK = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Wait 10 ms WRITE 40h ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Verify Wait 4 s READ DATA ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH INCREMENT CURRENT BLOCK NO DATA = 00h YES NO ++n = 1000 YES RP = VIH LAST BLOCK YES RP = VIH NO End ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI03472 55/57 Revision history M29W160FT, M29W160FB, M29W320FT, M29W320FB 10 Revision history Table 30. Date 26-Jun-2006 Document revision history Revision 1 Initial release. Document status promoted from Preliminary Data to full Datasheet. TFBGA48 6 x 8 mm package added. 80 ns speed class added. Voltage range extended when access time is 80 ns. Small text changes. Applied Numonyx branding. Changes 20-Jul-2007 2 26-Mar-2008 3 56/57 M29W160FT, M29W160FB, M29W320FT, M29W320FB Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved. 57/57 |
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